Terasic DE5a-Net Arria 10 GX FPGA Development Kit

March 22, 2018 | FPGA Machine Learning

In March 2018, Intel very kindly donated to my group a Terasic DE5a-Net Arria 10 GX FPGA Development Kit, though the Intel FPGA University Program. In this post, we document our initial experiments with the FPGA boards.

Hardware installation
Software Installation
Verifying the OpenCL environment

Hardware installation

1) Flip the DIP switch SW3.4 of the DE5a-Net-DDR4 FPGA board to the up position, so that when FPGA boots, it will load user-defined images rather than the factory default image.

2) Insert the FPGA board into a PCIe x8 slot in Venadi.

3) There is no 12V PCIe 6-pin power cable in Venadi, so the J3 power port on the FPGA board is not connected. This should be fine as long as our codes don’t use too many LEs nor run at very high speed.

4) Connect the mini USB port on the FPGA board to a USB port on the motherboard.

Software Installation

We plan to implement FPGA design mostly using OpenCL. Here we follow the instructions in DE5a-Net OpenCL User Manual to install the required software for OpenCL. Note Venadi runs CentOS 7.

1) Download Intel FPGA SDK for OpenCL 16.1. Note as of this writing, the latest version is 17.1. However, Terasic only provides Board Support Package (BSP) for v16.1.

2) Run setup_pro.sh to install Intel FPGA SDK for OpenCL with Quartus Prime Pro Edition. The software was installed in /bigdata/intelFPGA_pro/16.1/.

3) Download DE5a-Net-DDR4 openCL BSP (Board Support Package) from http:/de5a-net-ddr4.terasic.com/cd. Decompress the tarball DE5ANET_DDR4_OpenCL_BSP_16.1.tar.gz to the de5a_net_ddr4 folder under the folder /bigdata/intelFPGA_pro/16.1/hld/board.

4) Install the OpenCL license file 1-JOQ28R_License.dat in /bigdata/intelFPGA_pro/16.1/hld.

5) Change the permission for USB-Blaster II by creating the /etc/udev/rules.d/51-usbblaster.rules file, with the following content:

# USB-Blaster
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6002", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6003", MODE="0666"
# USB-Blaster II
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6010", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6810", MODE="0666"

6) Configure the environment by appending the following lines to ~/.bashrc:

export QUARTUS_ROOTDIR="/bigdata/intelFPGA_pro/16.1/quartus"
export ALTERAOCLSDKROOT="/bigdata/intelFPGA_pro/16.1/hld"
export QSYS_ROOTDIR="/bigdata/intelFPGA_pro/16.1/quartus/sopc_builder/bin"
export AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/board/de5a_net_ddr4
export PATH=$PATH:$QUARTUS_ROOTDIR/bin:$ALTERAOCLSDKROOT/linux64/bin:$ALTERAOCLSDKROOT/bin:$ALTERAOCLSDKROOT/host/linux64/bin:$QSYS_ROOTDIR/bin
export LD_LIBRARY_PATH=$AOCL_BOARD_PACKAGE_ROOT/linux64/lib:$ALTERAOCLSDKROOT/host/linux64/lib:$AOCL_BOARD_PACKAGE_ROOT/tests/extlibs/lib
export QUARTUS_64BIT=1
export LM_LICENSE_FILE=$ALTERAOCLSDKROOT/1-JOQ28R_License.dat

Verifying the OpenCL environment

1) List target board:

# aoc --list-boards
Board list:
  de5a_net_ddr4

2) Install and load the PCIe driver:

[root@venadi de5a_net_ddr4]# aocl install
aocl install: Running install from /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/linux64/libexec
Looking for kernel source files in /lib/modules/3.10.0-327.36.1.el7.x86_64/build
Using kernel source files from  /lib/modules/3.10.0-327.36.1.el7.x86_64/build
Building driver for BSP with name de5a_net_ddr4
make: Entering directory `/usr/src/kernels/3.10.0-327.36.1.el7.x86_64'
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci_queue.o
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci.o
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci_fileio.o
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci_dma.o
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci_pr.o
  CC [M]  /tmp/opencl_driver_7QqUQm/aclpci_cmd.o
  LD [M]  /tmp/opencl_driver_7QqUQm/aclpci_de5a_net_ddr4_drv.o
  Building modules, stage 2.
  MODPOST 1 modules
  CC      /tmp/opencl_driver_7QqUQm/aclpci_de5a_net_ddr4_drv.mod.o
  LD [M]  /tmp/opencl_driver_7QqUQm/aclpci_de5a_net_ddr4_drv.ko
make: Leaving directory `/usr/src/kernels/3.10.0-327.36.1.el7.x86_64'

3) Flash the sample hello_world.aocx OpenCL image onto the startup configuration of the FPGA board:

# cd /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/tests/hello_world/bin/

# aocl flash aclde5a_net_ddr40 hello_world.aocx
aocl flash: Running flash from /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/linux64/libexec
sed: /bigdata/intelFPGA_pro/16.1/quartus/linux64/liblzma.so.5: no version information available (required by /lib64/libselinux.so.1)
6M
========================= Page Selection =========================
Please select the flash page where to store your FPGA configure data:
[0] Factory Image Location(Address 0x00040000), SW3.4 = "1" (Right Position)
[1] User Image Location(Address 0x02B40000), SW3.4 = "0" (Left Position)
Enter a digital number 0 or 1 (Or other values to exit the program) followed by pressing the "Enter" key:
1
Flash Programming...
Info: *******************************************************************
Info: Running Quartus Prime Convert_programming_file
    Info: Version 16.1.2 Build 203 01/18/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel MegaCore Function License Agreement, or other
    Info: applicable license agreement, including, without limitation,
    Info: that your use is for the sole purpose of programming logic
    Info: devices manufactured by Intel and sold by Intel or its
    Info: authorized distributors.  Please refer to the applicable
    Info: agreement for further details.
    Info: Processing started: Tue Mar 20 17:34:43 2018
Info: Command: quartus_cpf --convert flash.cof
Info (210033): Memory Map File flash.map contains memory usage information for file flash.pof
...
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Mar 20 17:39:38 2018
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 3355 megabytes
    Info: Processing ended: Tue Mar 20 17:39:38 2018
    Info: Elapsed time: 00:04:19
    Info: Total CPU time (on all processors): 00:00:37

4) Power-cycle the host (completely power off the host, then turn it back on), which is required for the new image to loaded on the FPGA board.

5) Run the dia utility:

# aocl diagnose
aocl diagnose: Running diagnose from /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/linux64/libexec

------------------------- acl0 -------------------------
Vendor: Terasic

Phys Dev Name  Status   Information

aclde5a_net_ddr40Passed   Arria 10 Reference Platform (aclde5a_net_ddr40)
                       PCIe dev_id = 2494, bus:slot.func = 04:00.00, Gen3 x8
                       FPGA temperature = 51.9609 degrees C.

DIAGNOSTIC_PASSED
---------------------------------------------------------

6) Test the hello_world OpenCL image:

# cd /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/tests/hello_world/bin/
# aocl program aclde5a_net_ddr40 hello_world.aocx
aocl program: Running program from /bigdata/intelFPGA_pro/16.1/hld/board/de5a_net_ddr4/linux64/libexec
Programming device: de5a_net_ddr4 : Arria 10 Reference Platform (aclde5a_net_ddr40)
Reprogramming device [0] with handle 1
Program succeed.